(China (Mainland))
Product Summary
The XC4013E1PQ208C is a field programmable gate array, implemented with a regular,flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs). The XC4013E1PQ208C has generous routing resources to accommodate the most complex interconnect patterns.
Parametrics
XC4013E1PQ208C absolute maximum ratings: (1)Power-On Reset, TPOR: 10 to 33 ms; (2)Program Latency, TPI: 30 to 200 ms per CLB column; (3)CCLK (input) Delay (required), TICCK: 4 μs; (4)CCLK (input) Period (required), TCCLK: 100 ns.
Features
XC4013E1PQ208C features: (1)System featured Field-Programmable Gate Arrays: Select-RAMTM memory: on-chip ultra-fast RAM with; synchronous write option; dual-port RAM option; Fully PCI compliant (speed grades -2 and faster); Abundant flip-flops; Flexible function generators; Dedicated high-speed carry logic; Wide edge decoders on each edge; Hierarchy of interconnect lines; Internal 3-state bus capability; Eight global low-skew clock or signal distribution networks; (2)System Performance beyond 80 MHz; (3)Flexible Array Architecture; (4)Low Power Segmented Routing Architecture; (5)Systems-Oriented Features: IEEE 1149.1-compatible boundary scan logic support; Individually programmable output slew rate; Programmable input pull-up or pull-down resistors; 12 mA sink current per XC4000E output; (6)Configured by Loading Binary File: Unlimited re-programmability; (7)Read Back Capability: Program verification; Internal node observability; (8)Backward Compatible with XC4000 Devices; (9)Development System runs on most common computerplatforms: Interfaces to popular design environments; Fully automatic mapping, placement and routing; Interactive design editor for design optimization.
Diagrams
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 XC4000 |
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Negotiable |
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XC4000A |
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Negotiable |
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XC4000E |
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Negotiable |
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XC4000H |
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Negotiable |
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XC4000X |
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Negotiable |
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XC4000XL |
Other |
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Negotiable |
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