RC28F256P33T85

Product Summary

The RC28F256P33T85 is an Intel strataflash embedded memory. The RC28F256P33T85 is the latest generation of Intel StrataFlash memory device. Offered in 64-Mbit up through 1-Gbit densities, the P30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market segment. The benefits of the RC28F256P33T85 include more density in less space, high-speed interface, lowest cost-per-bit NOR device, and support for code and data storage. Features include high performance synchronousburst read mode, fast asynchronous access times, low power, flexible security options, and three industry standard package choices.

Parametrics

RC28F256P33T85 absolute maximum ratings: (1)Temperature under bias: -40℃ to +85℃; (2)Storage temperature: -65℃ to +125℃; (3)Voltage on any signal (except VCC, VPP): -0.5 V to +4.1 V; (4)VPP voltage: -0.2 V to +10 V; (5)VCC voltage: -0.2 V to +2.5 V; (6)VCCQ voltage: -0.2 V to +4.1 V; (7)Output short circuit current: 100 mA.

Features

RC28F256P33T85 features: (1)High performance: 85/88 ns initial access; 40 MHz with zero wait states, 20 ns clock-todata output synchronous-burst read mode; 25 ns asynchronous-page read mode; 4-, 8-, 16-, and continuous-word burst mode; Buffered Enhanced Factory Programming (BEFP) at 5μs/byte (Typ); 1.8 V buffered programming at 7μs/byte (Typ); (2)Architecture: Multi-Level Cell Technology: Highest Density; (3)at Lowest Cost; Asymmetrically-blocked architecture; Four 32-KByte parameter blocks: top or bottom configuration; 128-KByte main blocks; (4)Voltage and Power: VCC (core) voltage: 1.7 V to 2.0 V; VCCQ (I/O) voltage: 1.7 V to 3.6 V; Standby current: 55μA (Typ) for 256-Mbit; 4-Word synchronous read current: 13 mA (Typ) at 40 MHz; (5)quality and reliability|: operating temperature: -40℃ to +85℃·1-Gbit in SCSP is -30-℃ to +85℃; minimum 100,000 erase cycles per block; ETOXTM VIII process technology (130 nm); (6)Security: one-time programmable registers: 64 unique factory device identifier bits; 64 user-programmable OTP bits; Additional 2048 user-programmable OTP bits; selectable OTP Space in Main Array: 4x32KB parameter blocks + 3x128KB main blocks (top or bottom configuration); absolute write protection: VPP = VSS; Power-transition erase/program lockout; individual zero-latency block locking; individual block lock-down; (7)Software: 20μs (Typ) program suspend; 20μs (Typ) erase suspend; intelr flash data integrator optimized; basic command Set and extended command set compatible; common flash interface capable; (8)Density and Packaging: 64/128/256-Mbit densities in 56-Lead TSOP; (9)package; 64/128/256/512-Mbit densities in 64-Ball IntelR Easy BGA package; 64/128/256/512-Mbit and 1-Gbit densities in IntelR QUAD+ SCSP; 16-bit wide data bus.

Diagrams